In the past decade, signal and data processing aboard spacecraft has advanced rapidly from KIPS or thousands of instructions per second to MIPS or millions of instructions per second and are approaching GIPS or billions of instructions per second. The result is the utilization of increasingly powerful commercial technology that has to be adapted for space applications. The use of this technology in on-board processing permits repairable and reconfigurable systems in space. Such systems are described in U.S. patent application Ser. No. 10/334,317, filed Dec. 31, 2002 by Joseph Marshall, Alan F. Dennis, Charles A. Dennis and Steven G. Santee, assigned to the assignee hereof and incorporated herein by reference.
As is common in the design of electronics carried in space vehicles, a massive amount of redundancy has heretofore been utilized such that if one of the particular processing systems goes down due to massive incoming radiation or component failures, it was the policy to provide for redundant processing to repair the electronics by simply duplicating it and calling up the duplicate processor. Another approach is to utilize reconfigurable spaceborne processors and to reprogram and/or reconfigure these processors from the ground in the case of malfunction or a change in mission.
There are five areas of vulnerability in spaceborne applications due to either naturally occurring radiation or radiation which is the result of a nuclear release. Foremost in vulnerability are reconfigurable processors that are reprogrammed remotely from a ground station where the processors themselves are subject to damage due to radiation. Secondly, an area of vulnerability is the startup read-only memory or ROM for the processors, which if damaged will cause system failure when their contents are read.
Thirdly, the reconfigurable systems which use field programmable gate arrays or FPGAs are vulnerable. Fourth, vulnerability exists for systems that are utilized to store a shadow state which provides backup in case of errors or nuclear events so that the system can be recovered.
Finally, vulnerability exists for single-chip reconfigurable systems in which all of the reconfigurable and other components are on a single board in which all components are packaged into a single element.
More particularly, as to the need for reconfiguration in space systems, until recently, satellites have incorporated only limited on-board processing. The majority of data was passed through the satellite and transmitted to a terrestrial processing facility, limited primarily by the bandwidth of the down link. This lack of autonomy and on-board signal processing was driven primarily by technology limitations, as the power required to perform complex signal processing on flight was beyond the capacity of the satellite to provide it.
Note that the newest space systems have significantly more processing capability and seldom have enough external bandwidth or size, weight and power margin to perform all their missions reliably using all unique processing elements for each processing or recovery need. This increase in processing requirements also requires reducing redundancy used to combat component failures. This reduced redundancy requires better radiation hardening.
The migration to 0.15 micron radiation hardened technology at space foundries combined with hardened by design techniques and the continuing positive Total Ionizing Dose results on many commercial semiconductor lines ensure that there are many technologies to consider when constructing a space processing subsystem. However, utilizing 0.15 micron radiation hardening technology is not sufficient.
As to the need for better reconfigurable technology for space, to mitigate upsets, RAM-based FPGAs employ internal triple modular redundancy (TMR) and configuration read-back and compare of the configuration storage. Each of these elements is necessary for the reconfigurable systems.
In the past, reconfigurable technology for space includes fuse-based FPGA, SRAM-based FPGA, FLASH-based FPGA, and FLASH-based memory.
As to existing reconfiguration technologies, all of them are subject to failure in the presence of high radiation levels which can occur in space or which are the result of a nuclear event. Two popular configuration and reconfiguration technologies include competing FPGA approaches that are currently being used for spaceborne applications, i.e., fuse-based and SRAM-based technology. Fuse technology has historically been used because of the superior power/performance associated with fused configuration. The hard-wired fuse approach also eliminates the ability to upset the configuration data through single event effects (SEE) upset, although faults can be introduced into the logic functions of the FPGAs as well as into on-chip SRAM arrays. While both technologies support the use of triple-modular redundancy to combat SEE such as latch up, gate rupture or upset, better radiation resistance is required to eliminate the complexity, real estate, weight and power requirements of the triple modular redundancy. However, only the SRAM-based FPGA can be reconfigured.
Also, triple modular redundancy does not solve the underlying problem of avoiding damage due to radiation. Redundancy only applies to switching to undamaged circuits in the event of malfunction. Typically, for FPGAs, a soft reset is required to remove a single event function interrupt (SEFI), which necessitates a reload of the FPGA configuration data from an external source.
While the SRAM-based FPGA is field-programmable, its storage is volatile. As a result, external non-volatile memories are typically added externally to load the FGPA programming data upon power-up.
As to non-volatile FLASH memory and FPGA technologies, the most widely available non-volatile memory technology is FLASH, which comes in two variations, NAND-based and NOR based. Both FLASH technologies employ a dual gate structure with a control gate for programming the FLASH and a floating gate that acts as the non-volatile storage element. Charge pumps are employed to generate high voltages needed to write and erase the FLASH elements. In general, the NAND-based approach allows higher density, while the NOR-based approach supports more flexible programming methods and faster programming and read speeds.
However, radiation characterization of both varieties of FLASH memory chips has demonstrated SEE susceptibility in the control logic functions, where some of the write failures were attributed to upsets in the state machines and decoders. Other failures may have been caused by bus contention created from errors created within the control logic. Total Dose tolerance was also very limited.
Non-volatile FLASH-based FPGA products have been announced for commercial use, although they do not have sufficient radiation tolerance for spaceborne applications. The FLASH structure in the FPGA employs separate transistors that share the floating transistor. One is used to program the FLASH circuit and the other is used to configure the FPGA logic.
An anti-fuse radiation-tolerant product under development has been announced that incorporates triple-modular-redundancy storage elements directly into the logic blocks and an on-chip scrubbing circuit for the SRAM blocks, simplifying user efforts. However, as mentioned before, triple modular redundancy does not in and of itself offer radiation resistance but rather relies on costly redundancy if one part of a circuit is damaged.
Much of the recent work on FLASH, while not addressing radiation resistance, has been in the area of multilevel cell storage, which increases the amount of data that can be stored in a single FLASH cell to between two and four bits. This requires the ability to resolve analog voltages in a 2n ratio to the number of bits. While this increases density, there are tradeoffs in performance and the maximum number of program/erase cycles. Programming of NOR-based devices with Channel Hot Electrons (CHE) and either constant or ramped voltage programming has been successful for two bits/cell, although it requires program and verify overhead circuitry to extend to 3-4 bits/cell. Programming using Fowler-Nordheim Tunneling allows faster programming speeds at the expense of higher programming voltages than the Channel Hot Election approach, but suffers from limited data-retention time.
An advance in magnetic tunnel junction MRAM development was recently announced that eliminates adjacent bit disturbance and allows scaling to smaller geometries. The approach employs a write mode with two overlapping pulses that toggle the direction of the magnetic field. The technology requires that a write include a prior read sequence to determine which bits require toggling. A 4 Mb MRAM in 180 nm lithography is being produced using this technique. This technology is expected to have good radiation resistance though it will be harder to integrate with other technologies.
Although FeRAM continues to progress in the commercial arena with memories as large as 64 Mb in 130 nm lithography, radiation testing of several existing FeRAM devices demonstrated SEE sensitivity at a linear energy transfer, LET=20, rendering them unacceptable for most significant radiation environments.
None of the above storage and processing techniques address the fundamental problem of damage due to radiation and how radiation can damage a component by causing it to malfunction or to read in false data or instructions. When considering spaceborne applications, radiation hardening is thus of paramount concern.
By way of further background, chalcogenide technology has been used in the rewritable DVD and CD-ROM industries as illustrated by U.S. Pat. Nos. 6,730,384; 6,707,776; 6,683,739; and 6,670,016. Chalcogenide technology has also been used for non-radiation-hardened logic elements, switches and the like as illustrated in U.S. Pat. Nos. 6,707,087; 6,670,016; 6,660,136; 6,653,195; 6,709,887; 6,709,958; 6,710,423; 6,690,026; 6,737,312; 6,730,547; 6,586,921; 6,687,114; 6,653,193; and 6,737,726. In none of these patents is any radiation hardening property indicated. Moreover, U.S. Pat. No. 6,692,994 entitled “Method for manufacturing a programmable chalcogenide fuse within a semiconductor device,” assigned to the assignee hereof, describes fused semiconductor devices, but does not indicate the utility for radiation hardening.